In order to improve the density of the memory device, the industry has worked extensively at developing a method for reducing the size of a two-dimensional arrangement of memory cells. As the size of the memory cells of the two-dimensional (2D) memory devices continues to shrink, signal conflict and interference will significantly increase, so that it is difficult to perform operation of multi-level cell (MLC). In order to overcome the limitations of 2D memory device, the industry has developed a memory device having a three-dimensional (3D) structure, for example, using the BiCS (bit-cost Scalable) NAND configuration, the integration density is improved by arranging the memory cells on the substrate three-dimensionally, wherein the channel layer is vertically erected on the substrate, the gate is divided into three parts, namely a lower select gate layer, a middle control gate layer and an upper select gate layer, the crosstalk between signals can be reduced by distributing the gate signals into three groups of the gate electrodes.
The specific manufacturing processes of the above-described device generally include, depositing the lower select gate electrode layer on a silicon substrate, etching the lower select gate electrode layer to form trenches through to the substrate for further deposition of the lower portion of channel layer and the lead-out contact of the lower gate electrode, depositing the control gate layer on the lower select gate electrode layer, etching the control gate layer to form an intermediate channel region used for memory cell region and the lead-out contact for the middle control gate electrode, etching the control gate, dividing the whole device into a plurality of regions according to the word- and bit-line dividing requirements, depositing the upper select gate layer on the control gate layer and etching it, depositing to form the upper channel and the upper lead-out contact, then completing the device fabrication through the subsequent processes. In this process, the most critical etching step is merely the lithography of the intermediate memory channel region and the lead-out contact at the intermediate layer, which directly determines the integration density and signal anti-jamming capability of the whole device.
In the above-described BiCS process, in order to facilitate the etching of contact holes in each layer for signal output, stepped word line forming process is adopted to deposit the multilayer structure, i.e., firstly, forming the widest photoresist PR1 at the top of multilayer laminated structures for defining the bottom structure. After forming the widest stair at the bottom via RIE etching the laminated structure, using the processes of UV lighting, laser irradiation, heating or chemical treatment to slim the photoresist, forming the second widest photoresist PR2 that is used to define the secondary bottom, forming the second widest stair at the secondary bottom via RIE etching the laminated structure, and then narrowing the photoresist again to create PR3 . . . , repeating above processing steps until the desired stepped laminated structure is formed finally.
However, such circulating process of stepped photoresist-slimming followed by stair-etching is facing increasing challenges as the number of dielectric layers is increased, namely the multilayer laminated structures become thicken. One factor is that each additional gate layer or insulating layer between gates correspondingly results in one more processing step for both photoresist-narrowing and stair-etching, so the time consumption and manufacturing cost grow up significantly due to the multiplication of processing steps. And if the number of layers is too large, photoresist will be damaged severely, even some fracture or distortion can occur at the edge of the stairs, not only resulting in increased time consumption due to new photoresist re-coating, but also leading to short circuit or open circuit due to pattern distortion at the intermediate layer. In addition, for each layer, the gate electrode is shared, therefore apart from one necessary lead-out contact hole, the rest area is wasted, which decreases the memory integration density.